URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include] - Rev 52

Rev	Log message	Author	Age	Path
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5386d 11h	/openrisc/trunk/orpsocv2/bench/sysc/include
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5400d 13h	/openrisc/trunk/orpsocv2/bench/sysc/include
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5419d 07h	/openrisc/trunk/orpsocv2/bench/sysc/include
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5470d 17h	/openrisc/trunk/orpsocv2/bench/sysc/include
6	Checking in ORPSoCv2	julius	5533d 06h	/openrisc/trunk/orpsocv2/bench/sysc/include