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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [Or1200MonitorSC.cpp] - Rev 63

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63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5422d 08h /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5469d 07h /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5508d 08h /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5509d 04h /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5523d 06h /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5542d 00h /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5593d 10h /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
6 Checking in ORPSoCv2 julius 5655d 23h /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp

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