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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocAccess.cpp] - Rev 862

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862 sysc: avoid using orpsoc internal classes directly

The problem with using the internal classes directly is
that you have to use the internally generated name,
this in itself is perhaps not such a big issue, the issue
is that the internal name changes when the underlaying verilog
design changes.
This works around this by using the classes through the
top module, which is part of the external api.		 stekern 4141d 20h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 5049d 16h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5081d 07h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5116d 03h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5166d 14h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5168d 00h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 5170d 07h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5394d 12h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5411d 10h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5512d 08h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5531d 02h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5582d 12h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
6 Checking in ORPSoCv2 julius 5645d 01h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp

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