URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc] - Rev 57

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5346d 15h	/openrisc/trunk/orpsocv2/bench/sysc
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5385d 15h	/openrisc/trunk/orpsocv2/bench/sysc
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5386d 12h	/openrisc/trunk/orpsocv2/bench/sysc
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5400d 14h	/openrisc/trunk/orpsocv2/bench/sysc
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5419d 08h	/openrisc/trunk/orpsocv2/bench/sysc
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5470d 18h	/openrisc/trunk/orpsocv2/bench/sysc
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5510d 12h	/openrisc/trunk/orpsocv2/bench/sysc
6	Checking in ORPSoCv2	julius	5533d 07h	/openrisc/trunk/orpsocv2/bench/sysc