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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Rev 348

Rev	Log message	Author	Age	Path
348	First stage of ORPSoCv2 update - more to come	julius	5051d 08h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5254d 13h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5338d 09h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5349d 02h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5411d 02h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
6	Checking in ORPSoCv2	julius	5525d 00h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v