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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 863

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863 ORPSoC: Add paramers to or1200-monitor for setting name and path of log files

Two small patches in one to make or1200-monitor more useful outside of orpsocv2:
- Setting log path with a parameter allows more flexible directory layout
- if the plusarg "testcase" is set at runtime, this is used to set a unique
prefix for the log files. Plusargs are currently not used in orpsocv2, so if
it is not set, the name falls back to the value of the parameter
TEST_NAME_STRING. The value of the parameter is set to the define
`TEST_NAME_STRING in the test bench top levele to avoid any changes to the
orpsocv2 scripts. With this, we can get rid of `include test-defines in
or1200_monitor.v

Signed-off-by: Olof Kindgren <olof@opencores.org>		 olof 4145d 20h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5130d 20h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5133d 01h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5182d 21h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5184d 21h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5545d 19h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5597d 05h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5641d 06h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
6 Checking in ORPSoCv2 julius 5659d 18h /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v

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