OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog] - Rev 351

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5087d 02h /openrisc/trunk/orpsocv2/bench/verilog
348 First stage of ORPSoCv2 update - more to come julius 5087d 06h /openrisc/trunk/orpsocv2/bench/verilog
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5287d 16h /openrisc/trunk/orpsocv2/bench/verilog
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5290d 10h /openrisc/trunk/orpsocv2/bench/verilog
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5314d 15h /openrisc/trunk/orpsocv2/bench/verilog
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5374d 06h /openrisc/trunk/orpsocv2/bench/verilog
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5384d 23h /openrisc/trunk/orpsocv2/bench/verilog
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5428d 05h /openrisc/trunk/orpsocv2/bench/verilog
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5446d 23h /openrisc/trunk/orpsocv2/bench/verilog
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5462d 10h /openrisc/trunk/orpsocv2/bench/verilog
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5498d 09h /openrisc/trunk/orpsocv2/bench/verilog
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5542d 10h /openrisc/trunk/orpsocv2/bench/verilog
6 Checking in ORPSoCv2 julius 5560d 22h /openrisc/trunk/orpsocv2/bench/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.