URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench] - Rev 51

Rev	Log message	Author	Age	Path
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5427d 16h	/openrisc/trunk/orpsocv2/bench
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5446d 10h	/openrisc/trunk/orpsocv2/bench
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5461d 21h	/openrisc/trunk/orpsocv2/bench
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5497d 21h	/openrisc/trunk/orpsocv2/bench
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5537d 15h	/openrisc/trunk/orpsocv2/bench
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5541d 21h	/openrisc/trunk/orpsocv2/bench
6	Checking in ORPSoCv2	julius	5560d 09h	/openrisc/trunk/orpsocv2/bench