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[/] [openrisc/] [trunk/] [orpsocv2/] [bench] - Rev 63

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63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5288d 01h /openrisc/trunk/orpsocv2/bench
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5335d 00h /openrisc/trunk/orpsocv2/bench
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5345d 17h /openrisc/trunk/orpsocv2/bench
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5374d 01h /openrisc/trunk/orpsocv2/bench
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5374d 21h /openrisc/trunk/orpsocv2/bench
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5388d 23h /openrisc/trunk/orpsocv2/bench
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5407d 17h /openrisc/trunk/orpsocv2/bench
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5423d 04h /openrisc/trunk/orpsocv2/bench
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5459d 03h /openrisc/trunk/orpsocv2/bench
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5498d 21h /openrisc/trunk/orpsocv2/bench
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5503d 04h /openrisc/trunk/orpsocv2/bench
6 Checking in ORPSoCv2 julius 5521d 16h /openrisc/trunk/orpsocv2/bench

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