OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench] - Rev 64

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5304d 13h /openrisc/trunk/orpsocv2/bench
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5314d 10h /openrisc/trunk/orpsocv2/bench
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5361d 09h /openrisc/trunk/orpsocv2/bench
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5372d 02h /openrisc/trunk/orpsocv2/bench
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5400d 10h /openrisc/trunk/orpsocv2/bench
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5401d 06h /openrisc/trunk/orpsocv2/bench
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5415d 08h /openrisc/trunk/orpsocv2/bench
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5434d 02h /openrisc/trunk/orpsocv2/bench
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5449d 13h /openrisc/trunk/orpsocv2/bench
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5485d 12h /openrisc/trunk/orpsocv2/bench
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5525d 06h /openrisc/trunk/orpsocv2/bench
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5529d 13h /openrisc/trunk/orpsocv2/bench
6 Checking in ORPSoCv2 julius 5548d 01h /openrisc/trunk/orpsocv2/bench

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.