| Rev |
Log message |
Author |
Age |
Path |
| 854 |
Add OR1200_OR32_LWS define to board specific or1200_defines.v |
stekern |
4366d 13h |
/openrisc/trunk/orpsocv2/boards/actel |
| 652 |
Fix make compile.tcl for actel backend |
yannv |
4783d 04h |
/openrisc/trunk/orpsocv2/boards/actel |
| 563 |
Search for external cores in <board>/modules path |
olof |
4899d 21h |
/openrisc/trunk/orpsocv2/boards/actel |
| 544 |
ORPSoC ordb1a3pe1500 update - adding SD card controller. |
julius |
4925d 08h |
/openrisc/trunk/orpsocv2/boards/actel |
| 542 |
ORPSoC scripts cleanup. Now centralised.
Documentation updated for ml501's SPI programming, noting issues with ISE12. |
julius |
4930d 22h |
/openrisc/trunk/orpsocv2/boards/actel |
| 530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4954d 08h |
/openrisc/trunk/orpsocv2/boards/actel |
| 503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4997d 19h |
/openrisc/trunk/orpsocv2/boards/actel |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4999d 23h |
/openrisc/trunk/orpsocv2/boards/actel |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
5001d 20h |
/openrisc/trunk/orpsocv2/boards/actel |
| 492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
5018d 06h |
/openrisc/trunk/orpsocv2/boards/actel |
| 486 |
ORPSoC updates, mainly software, i2c driver |
julius |
5031d 04h |
/openrisc/trunk/orpsocv2/boards/actel |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5035d 08h |
/openrisc/trunk/orpsocv2/boards/actel |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
5052d 13h |
/openrisc/trunk/orpsocv2/boards/actel |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
5056d 08h |
/openrisc/trunk/orpsocv2/boards/actel |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5061d 09h |
/openrisc/trunk/orpsocv2/boards/actel |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5087d 23h |
/openrisc/trunk/orpsocv2/boards/actel |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5095d 03h |
/openrisc/trunk/orpsocv2/boards/actel |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5101d 18h |
/openrisc/trunk/orpsocv2/boards/actel |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5114d 18h |
/openrisc/trunk/orpsocv2/boards/actel |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5123d 03h |
/openrisc/trunk/orpsocv2/boards/actel |
