| Rev |
Log message |
Author |
Age |
Path |
| 854 |
Add OR1200_OR32_LWS define to board specific or1200_defines.v |
stekern |
4211d 19h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 544 |
ORPSoC ordb1a3pe1500 update - adding SD card controller. |
julius |
4770d 14h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 542 |
ORPSoC scripts cleanup. Now centralised.
Documentation updated for ml501's SPI programming, noting issues with ISE12. |
julius |
4776d 03h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4799d 14h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4843d 00h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4845d 04h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4847d 01h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4880d 14h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4940d 08h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4946d 23h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4959d 23h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4972d 10h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4973d 10h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4973d 22h |
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog |
