URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] [par/] [bin] - Rev 479

Rev	Log message	Author	Age	Path
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4913d 15h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4915d 07h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin
449	ORPSoC - or1200_monitor.v additions enabling new experimental execution checks. Replace use of "clean-all" with "distclean" as make rule to clean things.	julius	4948d 02h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4983d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin