URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] [par] - Rev 496

Rev	Log message	Author	Age	Path
496	ORPSoC ml501 updates - increased frequency, updated documentation	julius	4863d 09h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4912d 15h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4914d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par
449	ORPSoC - or1200_monitor.v additions enabling new experimental execution checks. Replace use of "clean-all" with "distclean" as make rule to clean things.	julius	4947d 01h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4982d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5244d 17h	/par
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5247d 11h	/par