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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend] - Rev 530

Rev	Log message	Author	Age	Path
530	ORPSoC update Ethernet MAC Wishbone interface fixes Beginnings of software update. ML501 backend script fixes for new ISE	julius	4860d 09h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend
496	ORPSoC ml501 updates - increased frequency, updated documentation	julius	4910d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4959d 13h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4961d 04h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend
449	ORPSoC - or1200_monitor.v additions enabling new experimental execution checks. Replace use of "clean-all" with "distclean" as make rule to clean things.	julius	4993d 23h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5029d 03h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend