URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [ddr2_model.v] - Rev 412

Rev	Log message	Author	Age	Path
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5119d 15h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5174d 22h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5381d 07h	/ddr2_model.v