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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog] - Rev 655

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Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4620d 13h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4800d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4881d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4898d 04h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4940d 18h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4968d 19h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4972d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5027d 16h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog

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