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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog] - Rev 482

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Rev Log message Author Age Path
482 ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO buffer updates. Software changes. julius 5044d 09h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 5045d 11h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5088d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5116d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5119d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5174d 22h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog

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