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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench] - Rev 655

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Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4658d 02h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4837d 13h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4918d 13h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4935d 18h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4978d 07h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5006d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5009d 22h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5065d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5268d 19h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5271d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench

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