URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_ctrl.v] - Rev 480

Rev	Log message	Author	Age	Path
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	5064d 22h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_ctrl.v
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5139d 02h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_ctrl.v