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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sim/] [bin/] [Makefile] - Rev 425

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425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4949d 16h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4958d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4961d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
71 ORPSoC board builds, adding readmes julius 5216d 07h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5220d 13h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5223d 07h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile

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