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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if] - Rev 547

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Rev Log message Author Age Path
547 ORPSoC dbg_if fix for slow Wishbone slaves julius 4740d 11h /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5002d 14h /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5004d 04h /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5247d 10h /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5305d 02h /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5367d 02h /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5382d 13h /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if
6 Checking in ORPSoCv2 julius 5481d 01h /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if

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