Rev |
Log message |
Author |
Age |
Path |
482 |
ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO buffer updates. Software changes. |
julius |
4917d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4921d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4922d 12h |
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4929d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v |
435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4968d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v |
403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4996d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v |
363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5046d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v |
360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5048d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v |
358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5048d 16h |
/or1200_defines.v |
356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5049d 01h |
/or1200_defines.v |
348 |
First stage of ORPSoCv2 update - more to come |
julius |
5051d 11h |
/or1200_defines.v |
65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5278d 20h |
/or1200_defines.v |
63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5291d 12h |
/or1200_defines.v |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5333d 08h |
/or1200_defines.v |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5338d 12h |
/or1200_defines.v |
49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5411d 04h |
/or1200_defines.v |
6 |
Checking in ORPSoCv2 |
julius |
5525d 03h |
/or1200_defines.v |