| Rev |
Log message |
Author |
Age |
Path |
| 848 |
or1200: l.lws support
Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.
Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk> |
stekern |
4228d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4802d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4819d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4819d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4822d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4823d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4823d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4857d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4877d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4878d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4885d 13h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4917d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4923d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4945d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4950d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4950d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4952d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4954d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
4990d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5002d 12h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
