| Rev |
Log message |
Author |
Age |
Path |
| 482 |
ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO buffer updates. Software changes. |
julius |
5045d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
5049d 03h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
5049d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
5057d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5088d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5095d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5116d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
5121d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
5122d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5123d 13h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5125d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
5161d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5174d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5175d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5175d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/include |
