URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_tag.v] - Rev 476

Rev	Log message	Author	Age	Path
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	4924d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5050d 11h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5053d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_tag.v