URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dpram.v] - Rev 805

Rev	Log message	Author	Age	Path
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	5022d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	5050d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5168d 20h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5172d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dpram.v