URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dpram.v] - Rev 483

Rev	Log message	Author	Age	Path
483	ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance testing build.	julius	4904d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
482	ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO buffer updates. Software changes.	julius	4909d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4921d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5039d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5043d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dpram.v