URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_top.v] - Rev 483

Rev	Log message	Author	Age	Path
483	ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance testing build.	julius	5054d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
426	ORPSoC update Reverted back to previous OR1200 instruction cache. (...which...) Fixed or1200-except test failure on generic model. ML501 build not passing or1200-except test. Tried disabling burst on the bus (memory server doesn't support it yet) to no avail. To be continued...	julius	5122d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5130d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5189d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5192d 18h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ic_top.v