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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_mult_mac.v] - Rev 478

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Rev Log message Author Age Path
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 5099d 06h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5177d 22h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5179d 12h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5179d 21h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5180d 07h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5182d 16h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v

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