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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_wb_biu.v] - Rev 746

Rev	Log message	Author	Age	Path
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	5053d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	5055d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5180d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5182d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5182d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_wb_biu.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5185d 11h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_wb_biu.v