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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Rev 54

Rev	Log message	Author	Age	Path
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5356d 02h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5374d 03h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5389d 01h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5407d 19h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5459d 05h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5483d 02h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5498d 23h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5503d 06h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
36	Better clean rule in makefile	julius	5517d 06h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
6	Checking in ORPSoCv2	julius	5521d 18h	/openrisc/trunk/orpsocv2/sim/bin/Makefile