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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Rev 54

Rev	Log message	Author	Age	Path
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5344d 20h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5362d 21h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5377d 19h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5396d 13h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5448d 00h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5471d 21h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5487d 18h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5492d 00h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
36	Better clean rule in makefile	julius	5506d 01h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
6	Checking in ORPSoCv2	julius	5510d 12h	/openrisc/trunk/orpsocv2/sim/bin/Makefile