URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Rev 53

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5383d 09h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5398d 08h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5417d 02h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5468d 12h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5492d 09h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5508d 06h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5512d 13h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
36	Better clean rule in makefile	julius	5526d 13h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
6	Checking in ORPSoCv2	julius	5531d 00h	/openrisc/trunk/orpsocv2/sim/bin/Makefile