URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin] - Rev 51

Rev	Log message	Author	Age	Path
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5430d 06h	/openrisc/trunk/orpsocv2/sim/bin
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5449d 00h	/openrisc/trunk/orpsocv2/sim/bin
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5500d 10h	/openrisc/trunk/orpsocv2/sim/bin
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5524d 07h	/openrisc/trunk/orpsocv2/sim/bin
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5540d 04h	/openrisc/trunk/orpsocv2/sim/bin
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5544d 11h	/openrisc/trunk/orpsocv2/sim/bin
36	Better clean rule in makefile	julius	5558d 11h	/openrisc/trunk/orpsocv2/sim/bin
6	Checking in ORPSoCv2	julius	5562d 23h	/openrisc/trunk/orpsocv2/sim/bin