URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [board/] [include] - Rev 506

Rev	Log message	Author	Age	Path
506	ORPSoC or1200 interrupt and syscall generation test	julius	4978d 00h	/openrisc/trunk/orpsocv2/sw/board/include
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	5033d 06h	/openrisc/trunk/orpsocv2/sw/board/include
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5127d 20h	/openrisc/trunk/orpsocv2/sw/board/include
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5133d 01h	/openrisc/trunk/orpsocv2/sw/board/include