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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] [Makefile] - Rev 479

Rev	Log message	Author	Age	Path
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	5046d 18h	/openrisc/trunk/orpsocv2/sw/bootrom/Makefile
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5128d 09h	/openrisc/trunk/orpsocv2/sw/bootrom/Makefile
361	OPRSoCv2 - adding things left out in last check-in	julius	5175d 06h	/openrisc/trunk/orpsocv2/sw/bootrom/Makefile