URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [board] - Rev 488

Rev	Log message	Author	Age	Path
488	ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added.	julius	5026d 09h	/openrisc/trunk/orpsocv2/sw/tests/or1200/board
466	ORPSoC updates: Add new test to determine processor's capabilities. Fix up typo in example in spiflash app README	julius	5060d 15h	/openrisc/trunk/orpsocv2/sw/tests/or1200/board
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	5061d 14h	/openrisc/trunk/orpsocv2/sw/tests/or1200/board
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5093d 06h	/openrisc/trunk/orpsocv2/sw/tests/or1200/board
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	5126d 20h	/openrisc/trunk/orpsocv2/sw/tests/or1200/board
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5133d 06h	/openrisc/trunk/orpsocv2/sw/tests/or1200/board