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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-dctest.c] - Rev 483

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483 ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance testing build. julius 4885d 04h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4933d 14h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 4953d 05h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4973d 15h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
349 ORPSoCv2 update with new software and makefile update julius 5023d 15h /or1200-dctest.c

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