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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-except.S] - Rev 671

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Rev Log message Author Age Path
671 ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model julius 4549d 21h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4780d 09h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4940d 18h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4940d 19h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4952d 18h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4961d 04h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 4994d 03h /or1200-except.S
349 ORPSoCv2 update with new software and makefile update julius 5011d 05h /or1200-except.S

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