OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-mmu.c] - Rev 483

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
483 ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance testing build. julius 5096d 03h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 5104d 22h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 5112d 20h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5144d 12h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 5164d 04h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5184d 13h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5217d 12h /or1200-mmu.c
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5234d 10h /or1200-mmu.c
349 ORPSoCv2 update with new software and makefile update julius 5234d 14h /or1200-mmu.c

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.