| Rev |
Log message |
Author |
Age |
Path |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4931d 20h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4932d 15h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4939d 18h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4971d 10h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4978d 01h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4991d 01h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4991d 02h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
5003d 00h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
5005d 00h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5006d 06h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5008d 11h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
5011d 11h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim |
