OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw] - Rev 403

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5121d 21h /openrisc/trunk/orpsocv2/sw
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5124d 02h /openrisc/trunk/orpsocv2/sw
396 ORPSoCv2 final software fixes...for now. See updated README julius 5127d 01h /openrisc/trunk/orpsocv2/sw
395 ORPSoCv2 moving ethernet tests to correct place julius 5127d 02h /openrisc/trunk/orpsocv2/sw
394 ORPSoCv2 removing unused directories julius 5127d 02h /openrisc/trunk/orpsocv2/sw
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5127d 02h /openrisc/trunk/orpsocv2/sw
392 ORPSoCv2 software path reorganisation stage 1. julius 5127d 18h /openrisc/trunk/orpsocv2/sw
374 ORPSoCv2 adding some files forgotten from last checkin julius 5160d 01h /openrisc/trunk/orpsocv2/sw
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5160d 01h /openrisc/trunk/orpsocv2/sw
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5172d 08h /openrisc/trunk/orpsocv2/sw
361 OPRSoCv2 - adding things left out in last check-in julius 5173d 22h /openrisc/trunk/orpsocv2/sw
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5173d 22h /openrisc/trunk/orpsocv2/sw
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5174d 07h /openrisc/trunk/orpsocv2/sw
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5174d 17h /openrisc/trunk/orpsocv2/sw
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5175d 22h /openrisc/trunk/orpsocv2/sw
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5176d 23h /openrisc/trunk/orpsocv2/sw
349 ORPSoCv2 update with new software and makefile update julius 5177d 03h /openrisc/trunk/orpsocv2/sw
348 First stage of ORPSoCv2 update - more to come julius 5177d 03h /openrisc/trunk/orpsocv2/sw
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5380d 07h /openrisc/trunk/orpsocv2/sw
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5400d 06h /openrisc/trunk/orpsocv2/sw

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.