| Rev |
Log message |
Author |
Age |
Path |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5044d 19h |
/openrisc/trunk/orpsocv2/sw |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5045d 19h |
/openrisc/trunk/orpsocv2/sw |
| 349 |
ORPSoCv2 update with new software and makefile update |
julius |
5045d 23h |
/openrisc/trunk/orpsocv2/sw |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5045d 23h |
/openrisc/trunk/orpsocv2/sw |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5249d 04h |
/openrisc/trunk/orpsocv2/sw |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5269d 02h |
/openrisc/trunk/orpsocv2/sw |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5286d 00h |
/openrisc/trunk/orpsocv2/sw |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5327d 20h |
/openrisc/trunk/orpsocv2/sw |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5386d 23h |
/openrisc/trunk/orpsocv2/sw |
| 50 |
Adding or32_funcs.S |
julius |
5387d 03h |
/openrisc/trunk/orpsocv2/sw |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5405d 16h |
/openrisc/trunk/orpsocv2/sw |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5421d 04h |
/openrisc/trunk/orpsocv2/sw |
| 45 |
Orpsoc eth test fix and script error message update |
julius |
5428d 03h |
/openrisc/trunk/orpsocv2/sw |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5457d 03h |
/openrisc/trunk/orpsocv2/sw |
| 6 |
Checking in ORPSoCv2 |
julius |
5519d 15h |
/openrisc/trunk/orpsocv2/sw |
