URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw] - Rev 58

Rev	Log message	Author	Age	Path
58	ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up	julius	5372d 19h	/openrisc/trunk/orpsocv2/sw
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5431d 21h	/openrisc/trunk/orpsocv2/sw
50	Adding or32_funcs.S	julius	5432d 02h	/openrisc/trunk/orpsocv2/sw
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5450d 15h	/openrisc/trunk/orpsocv2/sw
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5466d 03h	/openrisc/trunk/orpsocv2/sw
45	Orpsoc eth test fix and script error message update	julius	5473d 02h	/openrisc/trunk/orpsocv2/sw
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5502d 02h	/openrisc/trunk/orpsocv2/sw
6	Checking in ORPSoCv2	julius	5564d 14h	/openrisc/trunk/orpsocv2/sw