URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2] - Rev 49

Rev	Log message	Author	Age	Path
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5407d 00h	/openrisc/trunk/orpsocv2
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5422d 12h	/openrisc/trunk/orpsocv2
45	Orpsoc eth test fix and script error message update	julius	5429d 11h	/openrisc/trunk/orpsocv2
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5458d 11h	/openrisc/trunk/orpsocv2
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5482d 08h	/openrisc/trunk/orpsocv2
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5498d 05h	/openrisc/trunk/orpsocv2
41	Update to or1k top	julius	5501d 06h	/openrisc/trunk/orpsocv2
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5502d 12h	/openrisc/trunk/orpsocv2
36	Better clean rule in makefile	julius	5516d 12h	/openrisc/trunk/orpsocv2
6	Checking in ORPSoCv2	julius	5520d 23h	/openrisc/trunk/orpsocv2