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[/] [openrisc/] [trunk] - Rev 77

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Rev Log message Author Age Path
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5307d 18h /openrisc/trunk
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5308d 17h /openrisc/trunk
75 Fixed toolchain script's cygwin ncurses check julius 5313d 20h /openrisc/trunk
74 Toolchain script fix for ncurses header checking julius 5331d 22h /openrisc/trunk
73 toolchain script error fix julius 5331d 23h /openrisc/trunk
72 Toolchain install script: or1ksim location changed, few tweaks julius 5334d 20h /openrisc/trunk
71 ORPSoC board builds, adding readmes julius 5351d 03h /openrisc/trunk
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5355d 08h /openrisc/trunk
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5355d 09h /openrisc/trunk
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5358d 00h /openrisc/trunk
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5358d 03h /openrisc/trunk
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5378d 01h /openrisc/trunk
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5382d 07h /openrisc/trunk
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5385d 02h /openrisc/trunk
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5394d 23h /openrisc/trunk
62 This material is part of the separate website downloads directory. jeremybennett 5406d 03h /openrisc/trunk
61 The build directory should not be part of the SVN configuration. jeremybennett 5406d 03h /openrisc/trunk
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5412d 20h /openrisc/trunk
59 Toolchain install script gcc patch change and gdb configure change julius 5433d 21h /openrisc/trunk
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5436d 19h /openrisc/trunk

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