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Rev Log message Author Age Path
130 Updating uclibc patch julius 5139d 08h /openrisc
129 Previous commit was before saving file. jeremybennett 5140d 05h /openrisc
128 Tagging the 0.4.0rc2 candidate release of Or1ksim jeremybennett 5140d 05h /openrisc
127 New config option to allow l.xori with unsigned operand. jeremybennett 5140d 05h /openrisc
126 More explanation of l.xori. jeremybennett 5140d 06h /openrisc
125 Update to specification of l.xori. jeremybennett 5140d 12h /openrisc
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5141d 01h /openrisc
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5141d 05h /openrisc
122 Added l.ror and l.rori with associated tests. jeremybennett 5142d 01h /openrisc
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5142d 02h /openrisc
120 Documents exception generation by l.jalr and l.jr jeremybennett 5142d 02h /openrisc
119 Updated to clarify exceptions for division and details of multiplication. jeremybennett 5142d 13h /openrisc
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5142d 22h /openrisc
117 Updates on l.ff1, l.fl1 and l.maci. jeremybennett 5145d 01h /openrisc
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5145d 02h /openrisc
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5146d 01h /openrisc
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5146d 02h /openrisc
113 Updates to exception handling for l.add and l.div jeremybennett 5147d 01h /openrisc
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5147d 01h /openrisc
111 Changed conditionals for Verilator to "verilator" instead of "VERILATOR". jeremybennett 5147d 06h /openrisc

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