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132 This fixes files formatted with DOS line endings (something that should be sorted out outside SVN). jeremybennett 5153d 13h /openrisc
131 This brings the OpenRISC repository for GDB 6.8 into line with the patched
tool which is distributed. Missing Makefile.in and configure files are added.		 jeremybennett 5153d 13h /openrisc
130 Updating uclibc patch julius 5154d 16h /openrisc
129 Previous commit was before saving file. jeremybennett 5155d 12h /openrisc
128 Tagging the 0.4.0rc2 candidate release of Or1ksim jeremybennett 5155d 13h /openrisc
127 New config option to allow l.xori with unsigned operand. jeremybennett 5155d 13h /openrisc
126 More explanation of l.xori. jeremybennett 5155d 13h /openrisc
125 Update to specification of l.xori. jeremybennett 5155d 20h /openrisc
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5156d 09h /openrisc
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5156d 13h /openrisc
122 Added l.ror and l.rori with associated tests. jeremybennett 5157d 09h /openrisc
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5157d 09h /openrisc
120 Documents exception generation by l.jalr and l.jr jeremybennett 5157d 10h /openrisc
119 Updated to clarify exceptions for division and details of multiplication. jeremybennett 5157d 21h /openrisc
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5158d 06h /openrisc
117 Updates on l.ff1, l.fl1 and l.maci. jeremybennett 5160d 09h /openrisc
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5160d 09h /openrisc
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5161d 09h /openrisc
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5161d 10h /openrisc
113 Updates to exception handling for l.add and l.div jeremybennett 5162d 09h /openrisc

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