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425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 5106d 15h /openrisc
424 C++ library, needed for C++ compiler. jeremybennett 5107d 01h /openrisc
423 Minor typo fixed. jeremybennett 5107d 04h /openrisc
422 Separates out --force actions, so only build dirs corresponding to targets being built are blown away. jeremybennett 5107d 04h /openrisc
421 Fixing some typos in bld-all.sh's --help printout and changed all
"cd .." lines to "cd -".		 julius 5110d 02h /openrisc
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 5112d 00h /openrisc
419 ORPmon: Fixed interrupt routines in reset.S so they are compatible with new
GCC port (skip over redzone).
Added some defines to easily switch what is done when an error vector
is executed.
Added ability to print out EPCR when crashing.
Changed linker script back to one which doesn't skip over holes in SPI
flash memories.		 julius 5112d 03h /openrisc
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 5112d 03h /openrisc
417 ORPSoC re-adding doc automake files, this time not symlinks julius 5115d 00h /openrisc
416 ORPSoC doc cleanup - removing symlinks from automake'd docs build path julius 5115d 00h /openrisc
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5115d 00h /openrisc
414 Updates to add -mredzone and improved GCC optimizations. jeremybennett 5115d 19h /openrisc
413 Fixed to combined bug in the assembler and linker. jeremybennett 5116d 22h /openrisc
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5118d 14h /openrisc
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 5119d 02h /openrisc
410 ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again.		 julius 5120d 01h /openrisc
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 5120d 02h /openrisc
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5120d 14h /openrisc
407 Update or1ksim version in toolchain script to rc2 julius 5120d 17h /openrisc
406 ORPmon indented files, bus, align and instruction errors vectors printf and reboot julius 5120d 17h /openrisc

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