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858 orpsoc/tests: Fix or1200-dsxinsn when caches are not present

This test would go into an endless loop when caches are not present.		 stekern 4106d 13h /openrisc
857 orpsocv2: remove reference to r32 in context save/restore julius 4116d 03h /openrisc
856 Fixed rounding of UART divisor skrzyp 4160d 06h /openrisc
855 Publish OR1K 1.0 architecture spec julius 4203d 05h /openrisc
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4212d 22h /openrisc
853 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4238d 07h /openrisc
852 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4238d 08h /openrisc
851 changed branch delay flags skrzyp 4241d 07h /openrisc
850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4252d 23h /openrisc
849 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4252d 23h /openrisc
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4252d 23h /openrisc
847 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4252d 23h /openrisc
846 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4252d 23h /openrisc
845 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4252d 23h /openrisc
844 skrzyp 4253d 16h /openrisc
843 Applied RDiez suggestions skrzyp 4253d 17h /openrisc
842 Moving GDB 7.1 into the old collection. jeremybennett 4255d 15h /openrisc
841 GDB 7.2 is now considered the stable version. jeremybennett 4255d 15h /openrisc
840 Relocate GDB 6.8 to the old directory. jeremybennett 4255d 15h /openrisc
839 Forgot about updating linker flags, thanks RDiez! skrzyp 4256d 18h /openrisc

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